In the fabrication of integrated circuits, numerous integrated circuits are typically constructed simultaneously on a single semiconductor wafer. The wafer is then later subjected to a singulation process in which individual integrated circuits are singulated from the wafer. At certain stages of fabrication, it is often necessary to polish a surface of the semiconductor wafer. In general, a semiconductor wafer can be polished to remove high topography, surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. This polishing process is often referred to as mechanical planarization and is utilized to improve the quality and reliability of semiconductor devices. This process is usually performed during the formation of various devices and integrated circuits on the wafer.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This polishing process is often referred to as chemical mechanical planarization (CMP).
In general, the CMP process involves holding and rotating a thin flat wafer of semiconductor material against a wetted polishing surface under controlled pressure and temperature. FIG. 1 shows a conventional CMP device 10 having a rotatable polishing platen 12, a polishing head assembly 14, and a chemical supply system 16. Platen 12 is rotated at a preselected velocity by motor 18. Platen 12 is typically covered with a replaceable, relatively soft material 20 such as blown polyurethane, which may be wetted with a lubricant such as water.
Polishing head assembly 14 includes a polishing head (not shown) which holds semiconductor wafer 22 adjacent to platen 12. Polishing head assembly 14 further includes motor 24 for rotating the polishing head and semiconductor wafer 22, and a polishing head displacement mechanism 26 which moves semiconductor wafer 22 across platen 12 as indicated by arrows 28 and 30. Polishing head assembly 14 applies a controlled downward pressure, P, as illustrated by arrow 32 to semiconductor wafer 22 to hold semiconductor wafer 22 against rotating platen 12.
Chemical supply system 16 introduces a polishing slurry (as indicated by arrow 34) to be used as an abrasive medium between platen 12 and semiconductor 22. Chemical supply system 16 includes a chemical storage 36 and a conduit 38 for transferring the slurry from chemical storage 36 to the planarization environment atop platen 12.
Another apparatus for polishing thin flat semiconductor wafers is discussed in our U.S. Pat. No. 5,081,796. Other apparatuses are described in U.S. Pat. Nos. 4,193,226 and 4,811,522 to Gill, Jr. and U.S. Pat. No. 3,841,03 1 to Walsh.
One problem encountered in CMP processes is the non-uniform removal of the semiconductor surface. Removal rate is directly proportional to downward pressure on the wafer, rotational speeds of the platen and wafer, slurry particle density and size, slurry composition, and the effective area of contact between the polishing pad and the wafer surface. Removal caused by the polishing platen is related to the radial position on the platen. The removal rate is increased as the semiconductor wafer is moved radially outward relative to the polishing platen due to higher platen rotational velocity. Additionally, removal rates tend to be higher at wafer edge than at wafer center because the wafer edge is rotating at a higher speed than the wafer center.
Another problem in conventional CMP processes is the difficulty in removing non-uniform films or layers which have been applied to the semiconductor wafer. During the fabrication of integrated circuits, a particular layer or film may have been deposited or grown in a desired uneven manner resulting in a non-uniform surface which is subsequently subjected to polishing processes. The thicknesses of such layers or films can be very small (on the order of 0.5 to 5.0 microns), thereby allowing little tolerance for non-uniform removal. A similar problem arises when attempting to polish warped surfaces on the semiconductor wafer. Warpage can occur as wafers are subjected to various thermal cycles during the fabrication of integrated circuits. As a result of this warpage, the semiconductor surface has high and low areas, whereby the high areas will be polished to a greater extent than the low areas. These and other problems plague conventional CMP processes.
The present invention provides a planarization process which significantly reduces the problems associated with non-uniform removal across the platen and uneven or warped surfaces of the semiconductor wafer.